1. Field
The embodiments described herein relate generally to circuit manufacturing and, more particularly, to clock gaters with a programmable delay.
2. Background
Integrated circuit devices are typically designed using a combination of computer-automated design techniques and manual design techniques. The portions of the design layout generated by computer-automated tools are commonly referred to as tiles, and the portions of the design layout manually generated by circuit designers are commonly referred to as macros.
In a synchronous digital system, the clock signal is used to define a time reference for the switching of data throughout the system. The clock distribution network (or clock tree, when this network forms a tree) distributes the clock signal(s) from a source point to all the elements that use the same clock. The clock signal is distributed to tiles as well as macros.
For a macro, the clock tree logic is placed and routed by custom design. On the other hand, within a tile it is common for the clock tree to be at least partially designed by computer-automated tools. An automated synthesis tool can generate a tree that starts with the core clock signal (CCLK) and branches to all of the state elements in the tile. As the circuit design progresses, the number of stages in the clock tree generated by the automated synthesis may change. The number of stages in a clock tree is an important parameter in circuit design, because it determines the delay of the clock signal. For example, a clock signal measured at a certain point in the circuit can be delayed in proportion to the number of stages it has to pass through.
The automated generation of clock trees may create complications during the design process. The design of computer generated tiles and the custom macros generally proceed at different rates and in different order. For example, it is common for some tile synthesis operations to occur after the macro designs have been completed. One of these synthesis operations may yield a change in the number of stages in the clock tree. This change in turn may require the manual redesign of the macros to accommodate this change in clock signal delays.
In order to simulate the integrated circuit device operation during the design process, the clock trees in the macros need to be consistent with those in the tiles. Also, consistency is required for the final design. Adjustments to maintain clock delay consistency require significant time and effort, and may need to be repeated several times during the design phase.